# SR Latch

(Redirected from W1018)
Gate latch

## Curriculum

 Coder Merlin™  Computer Science Curriculum Data Unit: Boolean algebra Experience Name: SR Latch (W1018) Knowledge and skills: §10.332 Demonstrate understanding and proficiency in the use of SR latches Topic areas: Boolean algebra Classroom time (average): 30 minutes Study time (average): 60 minutes Successful completion requires knowledge: understand the construction and use of SR latches as the conceptual basis for memory Successful completion requires skills: demonstrate proficiency in constructing and using SR latches

## Background

Our memory enables us to remember an event after the original stimulus is gone. A latch is a device used to fasten something into place. In the case of an SR Latch, the role is to latch a single, binary digit enabling it to remember a value even after the original value (stimulus) is no longer present.

## Introduction

We've learned a lot about Boolean algebra and logic gates and how composition enables us to construct complex functionality from simple components. However, all functionality which we've considered so far presents an instantaneous value for output based upon the current input values. One of the most basic requirements of a computer is an ability to remember (or store) values for later use. This experience will describe one means of storing values by building a latch out of the logic gates with which we are already familiar.

## The SR Latch

In electronics, a latch is a circuit that has two stable states and can be used to store information. One of the most fundamental of these latches is an SR Latch. An SR Latch is able to capture its input value and preserve that value for use at a later time. An SR Latch has two inputs: The first is labeled set (or just S); its role is to set the output ${\displaystyle Q}$ high, or true; the second is labeled reset (or just R); its role is to reset the output ${\displaystyle Q}$ to make it low, or false. ${\displaystyle {\overline {Q}}}$ will always be the negated value of ${\displaystyle Q}$. The interesting aspect of a latch, however, is that when we set both set and reset to low. In this case, the latch will hold the previous value, i.e. the new value of ${\displaystyle Q}$ at time t, ${\displaystyle Q_{t}}$, will be equal to the value at time t-1, ${\displaystyle Q_{t-1}}$.

Reset Set State ${\displaystyle Q_{t}}$ ${\displaystyle {\overline {Q_{t}}}}$
0 0 Latch ${\displaystyle Q_{t-1}}$ ${\displaystyle {\overline {Q_{t-1}}}}$
0 1 Set 1 0
1 0 Reset 0 1
1 1 Forbidden undefined undefined

An SR Latch may be easily constructed using two NOR gates:

Note that the SR Latch relies on feedback in order to maintain its state.

## SR Latch Graph

Carefully consider the following SR Latch graph:

The x-axis indicates the time, in milliseconds, progressing rightward. The y-axis indicates the voltage, individually, for S (Set), R (Reset), and Q (output). In table form, this would appear as:

Time (ms) S (Set) R (Reset) Q (Output)
0 H L H
10 L L H
20 L L H
30 L H L
40 L H L
50 L L L
60 L L L
70 H L H
80 L L H
90 L L H
100 L L H

Observe the following state changes:

• At 0ms, S is high causing the output to go high (set).
• At 10ms, both S and R are low and the system enters a latch state. Because the previous output was high, it remains high (set).
• At 20ms, the system remains in a latch state. Because the previous output was high, it remains high (set).
• At 30ms, R is high causing the output to go low (reset).
• At 40ms, R remains high; the output remains low (reset).
• At 50ms, both S and R are low and the system enters a latch state. Because the previous output was low, it remains low (reset).
• At 60ms, the system remains in a latch state. Because the previous output was low, it remains low (reset).
• At 70ms, S is high causing the output to go high (set).
• At 80ms, both S and R are low and the system enters a latch state. Because the previous output was high, it remains high (set).
• At 90ms, the system remains in a latch state. Because the previous output was high, it remains high (set).
• At 100ms, the system remains in a latch state. Because the previous output was high, it remains high (set).

## Key Concepts

 Key Concepts An SR Latch is able to capture its input value and preserve that value for use at a later time An SR Latch has two inputs: set (or just S) reset (or just R) An SR Latch's output is labeled ${\displaystyle \color {White}Q}$ ${\displaystyle \color {White}Q}$ is set to high (set) when set (S) is high ${\displaystyle \color {White}Q}$ is set to low (reset) when reset (R) is high ${\displaystyle \color {White}Q}$ holds (latches) its previous value, when both S and R are low An SR Latch can be easily constructed using two NOR gates An SR Latch relies on feedback in order to maintain its state

## Exercises

 Exercises Visit the SR Latch in Falstad's editor here. Examine the output of an SR Latch, carefully toggling each of the inputs until you feel confident in your understanding of the latch.  M1018-10  Complete  Merlin Mission Manager  Mission M1018-10

## Excursions

 Excursions While an SR Latch is fully capable of remembering a single bit of information, it's generally not used to build a memory cell because it lacks the ability to perform synchronously with a clock signal. In order to synchronize the data with a clock signal, rather than use a latch, we generally use a device called a "flip-flop". One of the most basic designs is called a D-type Flip Flop. Research a D-type Flip Flop Construct a D-type Flip Flop using using only AND, OR, NOT, XOR, NOR, and NAND gates. Export each circuit using the File | Export As Text... option from the menu bar The text contains all of your work for the exercise. Select the entire text, copy it, and paste it into your journal using the correct excursion number. Answer the following questions: What additional functionality does a D-type Flip Flop provide that is unavailable in an SR Latch? How do the inputs to a D-type Flip Flop differ from the inputs of an SR Latch? How does a D-type Flip Flip protect against the forbidden state of an SR Latch?